Method and apparatus for measuring the duty cycle of a digital signal
US7333905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | May 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31726
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.