Method and system for device level simulation of large semiconductor memories and other circuits
US7333924B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jan 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors having unknown gate potentials, each CCR graph includes a top rail, and a bottom rail, and variable nodes, each of the transistors having unknown gate potential is modeled in the CCR graphs as a selectable resistor having a selected one of a first resistance and a much larger second resistance, and the method includes the steps of determining potentials at variable nodes of one of the CCR graphs with each selectable resistor of the graph having its first resistance (and also with each selectable resistor of the graph having its second resistance) without determining effective resistances between the variable nodes of the graph and the top rail or bottom rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.