Multiple data bus synchronization
US7334065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Aug 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion. The receiving circuit stores into a second FIFO, all second-stream multibit data portions that follow the identified second-stream multibit data portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.