Caching support for direct memory access address translation
US7334107B2 · kind B2 · utility
52Cited by
4References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jan 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.