Flexible and scalable architecture for transport processing
US7334132B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Sep 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/1675
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A transport processor that can be used in a digital audio-video receiver system comprises a front end and a memory interface. The front end receives concurrently a plurality of transport streams, where two or more of the plurality of transport streams can have different formats, and each transport stream includes a plurality of packets. The front end includes a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams. The memory interface is an interface through which the transport processor can store the aggregate transport stream in a memory for use by subsequent decode and display operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.