Optimization of integrated circuit device I/O bus timing
US7334148B2 · kind B2 · utility
3Cited by
28References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Mar 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.