Power fault handling method, apparatus, and system
US7334158B2 · kind B2 · utility
7Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Feb 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.