Method and system for detecting and correcting errors while accessing memory devices in microprocessor systems
US7334179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for ensuring data integrity in a data processing system may comprise monitoring when data for a specified device is available for error correction code generation, and receiving a first indication of the specified device, a second indication of the data, and a third indication of a size of the data during the monitoring. A new error correction code may be generated in hardware for the data based on the indicated size of the data and an indication may be provided to signal when generation of the new error correction code for a specified number of accesses for at least a portion of the data is complete. Detected errors may be corrected in software based on the newly generated error correction code. The first indication may be a device selection signal and the error correction code generation may be enabled or disabled via an enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.