Heterogeneously integrated microsystem-on-a-chip
US7335972B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2003 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Jun 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.