False lock protection in a delay-locked loop (DLL)
US7336112B1 · kind B1 · utility
93Cited by
11References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Δt) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Δt) is shorter than a desired delay period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.