High-speed latching technique and application to frequency dividers
US7336114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | May 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.