Organization of cache memory for hardware acceleration of the finite-difference time-domain method
US7337265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2004 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Jun 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an organization of cache memory for hardware acceleration of the FDTD method. The organization of cache memory for hardware acceleration of the FDTD method provides a substantial speedup to the finite-difference time-domain (FDTD) algorithm when implemented in a piece of digital hardware. The organization of cache memory for hardware acceleration of the FDTD method utilizes a very high bandwidth dual-port on-chip memory in a particular way. By creating many small banks of internal memory and arranging them carefully, all data dependencies can be statically wired. This allows for a many-fold speedup over SRAM-based solutions and removes the burden of data dependence calculation that streaming SDRAM-based solutions must perform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.