Hierarchical, programmable-priority content addressable memory system
US7337267B1 · kind B1 · utility
3Cited by
10References
49Claims
0Family size
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Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Feb 26, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical programmable-priority content addressable memory (CAM) system including first, second and third CAM devices. The first CAM device has a first priority number output and a first enable input. The second CAM device has a priority number input and an enable output coupled to the priority number output and the first enable input, respectively, of the first CAM device. The second CAM device also has a priority number output and an enable input. The third CAM device has a priority number input and an enable output coupled to the priority number output and the enable input, respectively, of the second CAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.