Body bias compensation for aged transistors
US7338817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Apr 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receive a body bias voltage; a programmable degradation monitor to detect aging of transistors, and a body bias voltage generator coupled to the circuit and the programmable degradation monitor. The body bias voltage generator to adjust the body bias voltage coupled into the circuit in response to transistor aging detected by the programmable degradation monitor. The programmable degradation monitor includes a reference ring oscillator, an aged ring oscillator, and a comparison circuit. The comparison circuit to compare data delays in the reference ring oscillator and the aged ring oscillator to detect transistor aging within the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.