Liquid crystal display panel with reduced parasitic impedance
US7339633B2 · kind B2 · utility
11Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Feb 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A liquid crystal display includes an array substrate, a data line, a gate line, a first and a second storage wiring, and a second substrate. The data line is disposed on the array substrate and intersects the gate line near a first pixel region. A second substrate, such as a color filter substrate, includes a second pixel region that corresponds to the first pixel region. The first storage wiring is positioned near an edge of the array substrate and the second storage wiring is disposed on the second substrate near an edge of the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.