Anti-fuse latch circuit and method including self-test
US7339848B1 · kind B1 · utility
13Cited by
28References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2006 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Jun 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable latch circuit (100) can include a programmable data circuit (104) with a data load path (116) that can enable a data value to be recalled into a volatile latch (102). A data load path (116) can be formed with devices (P100-P102) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.