Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals
US7340233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include a receiver and/or a transmitter that performs third order sub-harmonic conversion. The integrated circuit may include a Gilbert cell active mixer with three or more serially-connected transistors in each of the mixer's four branches. Alternatively, the integrated circuit may include a quad-ring passive resistive mixer with three or more serially-connected transistors in each of the mixer's four branches. Alternatively, the integrated circuit may include a logic circuit and a mixer. The logic circuit may apply logic operations to periodic logic signals having a local frequency and to delayed versions thereof to produce reference signals having a dominant spectral component at three times the local frequency. The mixer may mix input signals with the reference signals to produce output signals having a dominant spectral component at three times the local frequency less a center frequency of the input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.