On-chip bus
US7340548B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.