USB schedule prefetcher for low power
US7340550B2 · kind B2 · utility
11Cited by
5References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.