Fault processing for direct memory access address translation
US7340582B2 · kind B2 · utility
49Cited by
9References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.