Bios-level incident response system and method
US7340594B2 · kind B2 · utility
5Cited by
6References
24Claims
0Family size
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Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, apparatus, and method for depicting and responding to systematic problems and/or incidents in computing devices at a Basic Input/Output System level are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.