Power conservation techniques for a digital computer
US7340621B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer capable of playing real time applications includes a processing circuit configured to operate in a first power state, a second power state, and a third power state where the processing circuit consumes less power in the second state than in the first state, and less power in the third state than in the second state; and a real time subsystem coupled to the processing circuit, wherein the real time subsystem includes a buffer. The buffer is further configured to store data and output the data to an output device thereby enabling the processing circuit to enter the third power state while the buffer is outputting said data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.