Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources
US7340625B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Mar 31, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance is not critical. In one embodiment of apparatus the microprocessor is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator. In another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical. The shift in oscillator speed is mediated by a flip-flop latch circuit connected between one or more clock oscillators and the oscillator input of the controlled microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.