Real time clock architecture and/or method for a system on a chip (SOC) application
US7340634B2 · kind B2 · utility
3Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.