Method and apparatus for using memory compression to enhance error correction
US7340666B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2004 |
| Grant date | Mar 4, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for improving a memory's error detecting and error correcting capabilities. During operation, the system receives a data-word. Next, the system compresses the data-word into a compressed-word. If the amount of compression is greater than or equal to a compression-threshold, the system applies a strong error-correcting-code to the compressed-word to generate a coded-word. On the other hand, if the amount of compression is less than the compression-threshold, the system applies a weak error-correcting-code to the data-word to generate a coded-word. In either case the size of the coded-word is less than or equal to the size of a storage-word. The system then generates a flag that indicates the type of error-correcting code that was used to generate the coded-word. The system then stores the flag along with the coded-word in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.