Dynamic on-die termination launch latency reduction
US7342411B2 · kind B2 · utility
47Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.