Programmable low-power high-frequency divider
US7342429B2 · kind B2 · utility
1Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | May 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.