System and method for multi-channel delay cell based clock and data recovery
US7342521B1 · kind B1 · utility
9Cited by
6References
22Claims
0Family size
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Key dates
| Filing date | Jun 28, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jun 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed clock signal based on the reference clock signal. A dynamic link library clock and data recovery module reads and writes data flows contained within serialized data onto parallel data paths at a modified high speed clock signal based on the reference high speed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.