Shift register circuit
US7342568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.