Magnetic memory device, write current driver circuit and write current driving method
US7342822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Apr 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The number of write circuit components, variations in a write current flowing through each write line, and the power consumption for write operation can be reduced. A first constant current circuit and a second constant current circuit (a transistor (Q8) and a resistor (R4), and a transistor (Q7) and a resistor (R3)) are shared among a plurality of current direction control portions (54n−1, 54n, 54n+1, . . . ). The constant current circuits are connected to each current direction control portion (54) through a first circuit selector switch (SW1 . . . , SW1n, SW1n+1, . . . ) and a second circuit selector switch (SW2 . . . , SW2n, SW2n+1, . . . ) disposed for each current direction control portion (54). Moreover, a decode signal voltage is applied to the constant current circuits from a word decode line (16X) (bit decode line (16Y)) through the circuit selector switches (SW1) and (SW2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.