Data storage device and refreshing method for use with such device
US7342842B2 · kind B2 · utility
0Cited by
104References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 5, 2007 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.