Multi-standard variable block size motion estimation processor
US7342964B2 · kind B2 · utility
4Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2003 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jan 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of difference values by calculating an absolute difference between each pixel from a current block and a corresponding pixel from a reference block substantially simultaneously. The second circuit may be configured to generate a plurality of sum values by adding the difference values. The third circuit may be configured to generate at least one motion vector in response to the sum values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.