Digital PLL device
US7342986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2004 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S388/911
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.