Universal approach for simulating, emulating, and testing a variety of serial bus types
US7343279B2 · kind B2 · utility
3Cited by
17References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic apparatus for testing equipment for serial busses employs a generic bus model that breaks down a serial bus into separate layers that are managed by separate processors. The processors have parameters that can be programmed for communicating via one type of serial bus, or can be reprogrammed for communicating via another type of serial bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.