Processor having a finite field arithmetic unit utilizing an array of multipliers and adders
US7343472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational code, destination information, and source information. The instruction decoder is operably coupled to interpret the instruction to identify the arithmetic logic unit and/or the finite field arithmetic unit to perform the operational code of the corresponding instruction. The instruction decoder then identifies at least one destination location within the digital storage device based on the destination information contained within the corresponding instruction. The instruction decoder then identifies at least one source location within the digital storage device based on the source information of the corresponding instruction. When the finite field arithmetic unit is to perform the operational code, it performs a finite field arithmetic function upon data stored in the at least one source location in accordance with the operational code and provides the resultant to the destination location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.