Common built in test (BIT) software architecture
US7343520B2 · kind B2 · utility
1Cited by
9References
9Claims
0Family size
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Key dates
| Filing date | Apr 1, 2003 |
| Grant date | Mar 11, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for conducting a built in test on a system having a central processing unit (CPU), connected to one or more storage means, an input/output means and a plurality of assemblies PCI1, PCI2 . . . PCIN to be tested. A test initiator, generally a system wide operating system running on a system CPU, starts the test. Each of the assemblies to be tested has an identified and a test requirement, presented in a format common for, and applicable to, a plurality of central processing units and associated assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.