Power and ground buss layout for reduced substrate size
US7344227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2007 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Feb 20, 2027 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB41J2/14129
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
A semiconductor substrate for a micro-fluid ejection device. The substrate includes plurality of micro-fluid ejection actuators disposed adjacent a fluid supply slot in the semiconductor substrate. A plurality of power transistors, occupying a power transistor active area of the substrate, are disposed adjacent the ejection actuators and are connected through a first metal conductor layer to the ejection actuators. An array of logic circuits, occupying a logic circuit area of the substrate, is disposed adjacent the plurality of power transistors and is connected through a polysilicon conductor layer to the power transistors. A power conductor and a ground conductor for the ejection actuators is routed in a second metal conductor layer. The power conductor overlaps at least a portion of the power transistor active area of the substrate and the ground conductor overlaps at least a portion of the logic circuit area of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.