Electronic component and method for manufacturing the same
US7345362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Jan 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package is provided with a stepped level-difference in the inner wall surface, and an internal contact electrode formed on the upper surface of the stepped level-difference. At the bottom of the package is a shield electrode, on which a chip is mounted via an adhesion layer. The chip and the internal contact electrode are electrically connected by an interconnection wire. Location aligning for the chip and the interconnection wire, at least either one of these, is conducted by making use of a region, which is non-electrode portion, provided on the inner bottom surface of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.