Bias circuit for BJT amplifier
US7345547B2 · kind B2 · utility
25Cited by
14References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present invention include a bias circuit for a power-amplifying device, which receives and amplifies an input RF signal having a series of RF cycles within a modulation envelop. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.