Low-power SRAM memory cell
US7345909B2 · kind B2 · utility
108Cited by
7References
12Claims
0Family size
Inventors
Key dates
| Filing date | Sep 23, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read access transistor for selectively coupling a respective read bit line to a common connection node of a respective one of the first and second inverters, a switching transistor for selectively coupling the second inverter to a ground terminal, and a write access transistor for selectively coupling the common connection node of the second inverter to a write bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.