Generic modular multiplier using partial reduction
US7346159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Jul 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/725
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus multiplies a first and a second binary polynomial X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am−1tm−1+am−2tm−2tm−2+ . . . +a1t+a0, and where the coefficients ai are equal to either 1 or 0, and m is a field degree. The degree of X(t)<n, and the degree of Y(t)<n, and m≦n. The apparatus includes a digit serial modular multiplier circuit coupled to supply a multiplication result of degree ≧m of a multiplication of the first and second binary polynomials. The digit serial modular multiplier circuit includes a first and second register, each being ≦n bits. A partial product generator circuit multiplies a portion of digit size d of contents of the first register and contents of the second register. The partial product generator is also utilized as part of a reduction operation for at least one generic curve.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.