Apparatus for use in a computer systems
US7346722B2 · kind B2 · utility
1Cited by
24References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 20, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.