Memory controller and image forming device provided with the same
US7346752B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | May 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to output an active command to an SDRAM, at time t0, output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the active state at time t1. At time t3, the signal cs# returns to the negative state. At time t4 when some period of time has passed after time t3, output of the valid row address stops and the signal ras# enters the negative state. Outputs of the address signal adr and the control signals ras#, cas# and we# are controlled in synchronization with a modulated clock S-clk, which is generated at the spread spectrum generator. This reduces the electromagnetic interference that is caused by the address signal adr and the control signals ras#, cas# and we#.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.