Delaying lanes in order to align all lanes crossing between two clock domains
US7346795B2 · kind B2 · utility
3Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Feb 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.