Automatic built-in self-test of logic with seeding from on-chip memory
US7346823B1 · kind B1 · utility
12Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Sep 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Built-in self-test (BIST) devices and methods are disclosed. A BIST section (100) according to one embodiment can include a built-in seed value memory (150) that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory (150) to a test pattern generator (106) to generate multiple test patterns for scan chains (104-0 to 104-n). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.