Hardware acceleration of high-level language code sequences on programmable devices
US7346863B1 · kind B1 · utility
8Cited by
32References
27Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Feb 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A designer efficiently selects one or more code sequences for acceleration. A hardware accelerator is generated with multiple master ports to allow efficient access to memory. Profiling information can be provided to allow efficient selection of code sequences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.