CMOS transistor with high drive current and low sheet resistance
US7348248B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim gate spacer along a side of the gate electrode, and a source/drain region substantially aligned with an edge of the slim gate spacer. The source/drain region includes a first implantation region having an overlap with the gate electrode, a second implantation region further away from the channel region than the first implantation region, and a third implantation region further away from the channel region than the second implantation region. The source/drain region preferably further comprises an epitaxy region spaced apart from the slim gate spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.