Methods of forming reduced electric field DMOS using self-aligned trench isolation

US7348256B2 · kind B2 · utility

Assignee

• Atmel Corporation · US

Inventors

• Gayle W. Miller · Colorado Springs, US
• Volker Dudek · Ditzingen, DE
• Michael Graf · Leutenbach, DE

Key dates

• Filing date: Jul 25, 2005
• Grant date: Mar 25, 2008
• Expiry date: Jun 27, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.