Semiconductor package based on lead-on-chip architecture, the fabrication thereof and a leadframe for implementing in a semiconductor package
US7348660B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Dec 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.