Bi-directional bus buffer
US7348803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Sep 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.